Novel Ultra Low Power-Delay-Product Full Adder Cells in 45nm Fin-FET Technology
نویسندگان
چکیده
منابع مشابه
Design of Robust, Ultra Low-Power Efficient Full Adder Cell in sub-45nm Technologies
Nowadays, there is a need to design microelectronic circuits which utilizes less energy and small area because of extensive growth of portable devices like laptops, digital watches and personal communication devices like mobile phones, and continuous shrinking of technology node. Many applications require circuits of high throughput, small area and consume ultra-low power. In this regard, this ...
متن کاملUltra Low Power 1-Bit Full Adder
In this paper we propose a new 9 transistor 1-bit full adder. The proposed circuit performs efficiently in subthreshold region to employ in ultra low power applications. The main design objective for this new circuit is low power consumption and full voltage swing at a low supply voltage. The proposed cell also remarkably improves the power consumption, power delay product and has better noise ...
متن کاملLow Power Delay Product 10T Adder Circuit
In this paper, the various low power delay product full adder circuits have been analyzed. The adder is the fundamental blocks of any arithmetic circuit, so even a small reduction power or delay leads to improved performance of the circuit with optimal power saving. A 10T adder technique is the famous low power delay product full adder circuits with minimum transistor count. A new 10T technique...
متن کاملA Low Power Full Adder Cell based on Carbon Nanotube FET for Arithmetic Units
In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...
متن کاملA novel low-power full-adder cell for low voltage
This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Computing & Network Technology
سال: 2014
ISSN: 2210-1519
DOI: 10.12785/ijcnt/020204